Asynchronous circuit

An asynchronous circuit is a circuit in which the parts are largely autonomous. They are not governed by a clock circuit or global clock signal, but instead need only wait for the signals that indicate completion of instructions and operations. These signals are specified by simple data transfer protocols. This digital logic design is contrasted with a synchronous circuit which operates according to clock timing signals.

Contents

Theoretical foundations

Petri nets are an attractive and powerful model for reasoning about asynchronous circuits. However Petri nets have been criticized for their lack of physical realism (see Petri net: Subsequent models of concurrency). Subsequent to Petri nets other models of concurrency have been developed that can model asynchronous circuits including the Actor model and process calculi.

The term asynchronous logic is used to describe a variety of design styles, which use different assumptions about circuit properties. These vary from the bundled delay model - which uses 'conventional' data processing elements with completion indicated by a locally generated delay model - to delay-insensitive design - where arbitrary delays through circuit elements can be accommodated. The latter style tends to yield circuits which are larger than bundled data implementations, but which are insensitive to layout and parametric variations and are thus "correct by design".

Asynchronous logic is the logic required for the design of asynchronous digital systems. These function without a clock signal and so individual logic elements cannot be relied upon to have a discrete true/false state at any given time. Boolean logic is inadequate for this and so extensions are required. Karl Fant developed a theoretical treatment of this in his work Logically determined design in 2005 which used four-valued logic with null and intermediate being the additional values. This architecture is important because it is quasi-delay insensitive. [1] Scott Smith and Jia Di developed a ultra-low power variation of Fant's Null Convention Logic that incorporates multi-threshold CMOS.[2] This variation is termed Multi-threshold Null Convention Logic (MTNCL), or alternatively Sleep Convention Logic (SCL).[3] Vadim Vasyukevich developed a different approach based upon a new logical operation which he called venjunction. This takes into account not only the current value of an element, but also its history.[4]

Benefits

Different classes of asynchronous circuitry offer different advantages. Below is a list of the advantages offered by Quasi Delay Insensitive (QDI) circuits, generally agreed to be the most "pure" form of asynchronous logic that retains computational universality. Less pure forms of asynchronous circuitry offer better performance at the cost of compromising one or more of these advantages:

Disadvantages

Recent breakthrough

Sleep Convention Logic (SCL) overcomes most of the disadvantages listed above. Important advantages over Null Convention Logic (NCL) are that SCL is input incomplete and does not require observability. This eliminates previous incompatibilities of asynchronous architectures with standard electronic design automation (EDA) tools. In addition, SCL combines completion and sleep signals, reducing area overhead. Overall, design of logic using SCL results in speed and area comparable to synchronous architecture, with lower dyamic energy per operation, and lower leakage power. [11]

Asynchronous CPU

Asynchronous CPUs are one of several ideas for radically changing CPU design.

Unlike a conventional processor, a clockless processor (asynchronous CPU) has no central clock to coordinate the progress of data through the pipeline. Instead, stages of the CPU are coordinated using logic devices called "pipeline controls" or "FIFO sequencers." Basically, the pipeline controller clocks the next stage of logic when the existing stage is complete. In this way, a central clock is unnecessary. It may actually be even easier to implement high performance devices in asynchronous, as opposed to clocked, logic:

Asynchronous logic proponents believe these capabilities would have these benefits:

The biggest disadvantage of the clockless CPU is that most CPU design tools assume a clocked CPU (i.e., a synchronous circuit). Many tools "enforce synchronous design practices".[12] Making a clockless CPU (designing an asynchronous circuit) involves modifying the design tools to handle clockless logic and doing extra testing to ensure the design avoids metastable problems. The group that designed the AMULET, for example, developed a tool called LARD[13] to cope with the complex design of AMULET3.

Despite the difficulty of doing so, numerous asynchronous CPUs have been built, including:

The ILLIAC II was the first completely asynchronous, speed independent processor design ever built; it was the most powerful computer at the time.[14]

DEC PDP-16 Register Transfer Modules (ca. 1973) allowed the experimenter to construct asynchronous, 16-bit processing elements. Delays for each module were fixed and based on the module's worst-case timing.

The Caltech Asynchronous Microprocessor (1988) was the first asynchronous microprocessor (1988). Caltech designed and manufactured the world's first fully Quasi Delay Insensitive processor. During demonstrations, the researchers amazed viewers by loading a simple program which ran in a tight loop, pulsing one of the output lines after each instruction. This output line was connected to an oscilloscope. When a cup of hot coffee was placed on the chip, the pulse rate (the effective "clock rate") naturally slowed down to adapt to the worsening performance of the heated transistors. When liquid nitrogen was poured on the chip, the instruction rate shot up with no additional intervention. Additionally, at lower temperatures, the voltage supplied to the chip could be safely increased, which also improved the instruction rate—again, with no additional configuration.

In 2004, Epson manufactured the world's first bendable microprocessor called ACT11, an 8-bit asynchronous chip.[23][24][25][26][27] Synchronous flexible processors are slower, since bending the material on which a chip is fabricated causes wild and unpredictable variations in the delays of various transistors, for which worst case scenarios must be assumed everywhere and everything must be clocked at worst case speed. The processor is intended for use in smart cards, whose chips are currently limited in size to those small enough that they can remain perfectly rigid.

See also

References

  1. ^ Karl M. Fant (2005), Logically determined design: clockless system design with NULL convention logic (NCL), John Wiley and Sons, ISBN 9780471684787, http://books.google.co.uk/books?id=UTHFcdvvHQcC 
  2. ^ Smith, Scott and Di, Jia (2009). Designing Asynchronous Circuits using NULL Conventional Logic (NCL). Morgan & Claypool Publishers. ISBN 9781598299816. 
  3. ^ Scott, Smith and Di, Jia. "U.S. 7,977,972 Ultra-Low Power Multi-threshold Asychronous Circuit Design". http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7977972.PN.&OS=PN/7977972&RS=PN/7977972. Retrieved 12/12/2011. 
  4. ^ V.O.Vasyukevich (April, 2007), "Decoding asynchronous sequences", Automatic Control and Computer Sciences (Allerton Press) 41 (2): 93–99, doi:10.3103/S0146411607020058, ISSN 1558-108X, http://www.springerlink.com/content/e61016374u41p176/ 
  5. ^ "Epson Develops the World's First Flexible 8-Bit Asynchronous Microprocessor" 2005
  6. ^ Furber, Steve. "Principles of Asynchronous Circuit Design". Pg. 232. http://owlhouse.csie.nctu.edu.tw/~dannim/AsynCD/principles_of_ASYNC.pdf. Retrieved 12/13/2011. 
  7. ^ Furber, Steve. "Principles of Asynchronous Circuit Design". Pg. 232. http://owlhouse.csie.nctu.edu.tw/~dannim/AsynCD/principles_of_ASYNC.pdf. Retrieved 12/13/2011. 
  8. ^ "Keep It Strictly Synchronous: KISS those asynchronous-logic problems good-bye". Personal Engineering and Instrumentation News, November 1997, pages 53-55. http://www.fpga-site.com/kiss.html
  9. ^ van Leeuwen, T.M. (2010). Implementation and automatic generation of asynchronous scheduled data ow graph. Delft. http://ens.ewi.tudelft.nl/Education/msctheses/vanleeuwen-thesis.pdf. 
  10. ^ van Leeuwen, T.M. (2010). Implementation and automatic generation of asynchronous scheduled data ow graph. Delft. http://ens.ewi.tudelft.nl/Education/msctheses/vanleeuwen-thesis.pdf. 
  11. ^ Scott, Smith and Di, Jia. "U.S. 7,977,972 Ultra-Low Power Multi-threshold Asychronous Circuit Design". http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7977972.PN.&OS=PN/7977972&RS=PN/7977972. Retrieved 12/12/2011. 
  12. ^ "ASIC to FPGA migration"
  13. ^ LARD
  14. ^ a b c "In the 1950and 1960s, asynchronous design was used in many early mainframe computers, including the ILLIAC I and ILLIAC II ... ." Brief History of asynchronous circuit design
  15. ^ "The Illiac is a binary parallel asynchronous computer in which negative numbers are represented as two's complements." -- final summary of "Illiac Design Techniques" 1955.
  16. ^ "Entirely asynchronous, its hundred-odd boards would send out requests, earmark the results for somebody else, swipe somebody else's signals or data, and backstab each other in all sorts of amusing ways which occasionally failed (the "op not complete" timer would go off and cause a fault). ... [There] was no hint of an organized synchronization strategy: various "it's ready now", "ok, go", "take a cycle" pulses merely surged through the vast backpanel ANDed with appropriate state and goosed the next guy down. Not without its charms, this seemingly ad-hoc technology facilitated a substantial degree of overlap ... as well as the [segmentation and paging] of the Multics address mechanism to the extant 6000 architecture in an ingenious, modular, and surprising way ... . Modification and debugging of the processor, though, were no fun." "Multics Glossary: ... 6180"
  17. ^ "10/81 ... DPS 8/70M CPUs" Multics Chronology
  18. ^ "The Series 60, Level 68 was just a repackaging of the 6180." Multics Hardware features: Series 60, Level 68
  19. ^ a b c "A Network-based Asynchronous Architecture for Cryptographic Devices" by Ljiljana Spadavecchia 2005 in section "4.10.2 Side-channel analysis of dual-rail asynchronous architectures" and section "5.5.5.1 Instruction set"
  20. ^ "Handshake Solutions HT80C51" "The Handshake Solutions HT80C51 is a Low power, asynchronous 80C51 implementation using handshake technology, compatible with the standard 8051 instruction set."
  21. ^ SEAforth Overview "... asynchronous circuit design throughout the chip. There is no central clock with billions of dumb nodes dissipating useless power. ... the processor cores are internally asynchronous themselves."
  22. ^ "GreenArrayChips" "Ultra-low-powered multi-computer chips with integrated peripherals."
  23. ^ "Seiko Epson tips flexible processor via TFT technology" by Mark LaPedus 2005
  24. ^ "A flexible 8b asynchronous microprocessor based on low-temperature poly-silicon TFT technology" by Karaki et. al. 2005. Abstract: "A flexible 8b asynchronous microprocessor ACTII ... The power level is 30% of the synchronous counterpart."
  25. ^ "Introduction of TFT R&D Activities in Seiko Epson Corporation" by Tatsuya Shimoda (2005?) has picture of "A flexible 8-bit asynchronous microprocessor, ACT11"
  26. ^ "Epson Develops the World's First Flexible 8-Bit Asynchronous Microprocessor"
  27. ^ "Seiko Epson details flexible microprocessor: A4 sheets of e-paper in the pipeline by Paul Kallender 2005

External links